1. Field of the Invention
This invention relates generally to digital logic circuitry, and more particularly to an improved current mode clock pulse driver which is capable of producing a first set of individually enabled controllable pulse width clock signals having a first predetermined relationship to the pulses of the system clock applied to the driver and which circuit is also capable of producing a second and third set of clock pulse signals the pulse widths of the pulses of each of the second and third sets of signals are also controllable, said second and third sets of clock signals each having a predetermined relationship with the pulses of the clock signal applied to the pulse driver.
2. Description of the Prior Art
In synchronous digital data processing systems, digital signals representing data or instructions are stored in storage devices such as registers and such signals are transmitted between registers which are enabled, or strobed, by clock pulses, or strobes, which can also be used to enable, or strobe, active devices for manipulating or controlling digital signals. Examples of such active devices are switches, adders, comparators, arithmetic and logic units and the like. In larger high speed digital systems, the clock pulse signal from a precisely controlled oscillator, or the system clock, is distributed to many printed circuit boards or substrates to co-ordinate the activities of the system. Since not all of the paths traveled by the system clock are precisely the same length, the pulses of the system clock will arrive at different portions of the system at different times.
Certain actions in a clocked or synchronous system require less than a full clock, the period of time between adjacent leading edges of the clock pulses of the system clock. To improve the performance of the system clock., a second clock signal is frequently distributed having the same frequency as the system clock, however the leading edges of pulses of the second clock will be displaced in time, some predetermined amount, or period of time, with respect to the leading edges of the pulses of the system clock. The availability in a system of such a second clock pulse signal, or strobe, permits the designers of such digital data processing systems to improve performance or throughput of certain parts of the system for those operations in which the time for data signals to be operated on is less than the period T of the system clock.
A particular example in which the availability of a second clock pulse, or strobe, is useful occurs in the addressing of a random access memory such as a high speed cache where the register in which the address is stored is strobed, or enabled, by a register clock pulse and the data is written into or read from the addressed memory location by a write clock pulse, or strobe. To achieve maximum performance from such memories, and other elements of the data processing system it is also necessary to vary the pulse widths of the pulses of the register and write clock pulse signals.
The prior art larger high speed digital data processing systems have solved the problem of providing a second clock signal having the same frequency, or period, as the system clock by the use of delay lines to delay the second clock signal with respect to the system clock a fixed percentage of the period of the system clock. The second clock is then distributed throughout the system in the same manner as the system clock. The problem with such a solution is the difficulty in making the propagation delays of the signal in the transmission of the two clocks substantially the same throughout the system in order to maintain substantially constant the desired relationship between the leading edges, for example, of the two clock signals the same.
There is a need in large high speed digital data processing systems having a clock pulse rate, such that the periods of the signals is in the range of 25-50 nanoseconds, for a clock pulse driver to which a single clock signal at the desired frequency, the system clock, can be applied and which can produce a plurality of write pulses and a plurality of register pulses, the widths of the pulses of which are controllable and the delay with respect to the system clock is precisely controllable to provide the clock signals needed by a significant number, from 50 to 100 of integrated circuit chips which may be packaged together on a printed circuit board, or substrate, from a driver circuit which is also adapted to be mounted on such board or substrate.